Can you try something for me. At the lowest input voltage, say 1 A output measure the bias voltage. Then sweep the input voltage up to maximum (265 VAC). Let me know the results. The bias voltage should stay stable under this condition
if it changes linearly with input voltage then the bias winding is reversed. If it stay stable then please post your transformer design, winding order, and schematic for further digging.

Cheers

PI-Chekov

forgot to say do not think that CTR is related to the issue.

Cheers

PI-Chekov

The BIAS voltage stays stable at 25 Volts DC when I have a load of 1 Ampere and vary the input voltage from lowest to highest one.
My idea is that the BIAS winding is too much loaded which leads to voltage break down at zero load condition after full load condition on the output. Unfortunately the TOP247 needs a current flow into the control pin to shut off (0% Duty Cycle) and in opposite no or low current to open. The problem is that at no load (equal to shut down after a full load condition) there is no or only little energy pumped into the transformer to feed the BIAS current for the control pin. The control pin needs max. 8 mA (see data sheet p. 34) to go to 0% duty cycle (shut down). But there can flow much more current into the pin because it is not current limited.

Regards

Tony

Try increasing the bias winding cap value. I'd recommend going to 10 uF and see if that solves the problem. I agree if you go from full to zero load the switching frequency will drop while maximum current is drawn through the opto transistor from the bias winding (~6mA). A large bias cap should provide enough ride through.

Cheers

PI-Chekov

I tested with a 10 µF electrolytic capacitor. But it did not help a lot: With the 1 µF capacitor the voltage breaks down after a load change to no-load to about 6 Volts for 240 ms. With the 10 µF capacitor it breaks down a little bit slower but to 6 Volts too and for 200 ms. So it has become only a little bit better.

The ~ 6 mA control current is the current which is necessary to drive the TOP247 to 0% duty cycle. But on page 39, figure 51 I see, that the current into the control pin is not current limited. For example if you connect a 7 V voltage source to the pin there flows about 55 mA into the pin. So the pin would consum unnecessary much current resp. energy if you drive the optocoupler to much. And so my idea was that if I have an optocoupler with a to high CTR (current amplification) it would contribute to unnecessarily drive to a high current into the control pin.

But: If I assume a initial voltage of the 10µF capacitor of 30 Volts and a current load of 6 mA and there will be no more energy pumped into the capacitor, it will be discharged to 9 Volts after a time of 35 ms (dV / dt = I / C and 30V - 9V = 21V and ...). So I would need a much bigger capacitor to span the time:
I would need a (dV / dt) = 21V / 240ms = 87.5V/s which leads to a capacitance C = I / (dV/dt) = 6mA / 87.5V/s = 68.571 µF.
Is such a big value practicable or usual in that place?

Perhaps it is not necessary to hold up the bias voltage over 6 volts at 0% duty cycle because if the duty cycle is 0% there is nothing to control. If the duty cycle rises there is enough energy for the bias again and as a result for the control too?
On the contrary a too big capacitance would delay the bias voltage's rising when duty cycle rises from 0%.

Regards
Tony

Hello Tony11,

I agree with your analysis except for the time that the bias capacitor has to maintain the current into the control pin is much shorter than you assumed. For example a time of 35 ms would be equivalent to a 28 Hz switching frequency (the bias is refreshed every switching cycle).

Can you post your schematic? - there's something everyone has missed so far and I hope the schematic might help us.

Cheers

PI-Chekov

Hello PI-Chekov,

I am not allowed by my company to publish the schematic. It is derived from your applications.
I have tested the following: Disconnected the BIAS winding from the optocoupler and instead supplied the optocoupler (and so the control pin) with an external voltage supply with 15V. Then I have measured the voltage at the unconnected (=> unloaded) BIAS winding to see if there is enough voltage:
In the phase "no-load after full load" there is a peak of 20V. Rectified and filtered with a capacitor plus the control pin load makes that I have only 6V a BIAS.
On the other hand on picture 2 with full output load you can see a 70v peak which lead to a too high BIAS voltage.

Regard
Tony

Hello Tony,

understand about publishing - if acceptable you can send me a private message with the schematic.

The waveforms are great - appreciate the time in taking and labeling. Can you try something for me and show both the bias voltage waveform and the drain voltage waveform together. The scope probes would both be referenced to primary side ground (to which the SOURCE pin of PI part is connected) and then one probe to Drain and one to bias winding.

Cheers

PI-Chekov