Inductor for PFS716EG 350W

21 posts / 0 new

Hello,

 

we are using the PFS716EG as controller of a PFC stage providing 350W. We want to be abble to operate on the range 260VAC - 90VAC, but we are having problems on the range 160VAC-90VAC where the PFC is not being abble of work propertly, even it breaks in this condition.

 

We have used the PFS716EG spreadsheet in order to calculate the inductor we need on our stage, but depending on the type of  core, the inductance varies between 150uH and 3mH. Actually, we are using a custom 800uH but it seems is not enough.

 

Do you know wich is the best core type for our application? 

 

Do you know why our controller is not protecting himself and it breaks?

 

Thanks.

Sendust and Ferrite can all me made to work well, with minor pros and cons. 

Can you post the spreadsheet, and the layout?

Find attached the spreadsheet. Do you mean pcb gerbers? Thanks

Could you post an image (gif/tif/jpg), of the layout?

 

 

I can send you more information if you need. Thanks

I see multiple problems with the layout.

Pls. carefully review the layout recommendations in the datasheet and app note and correct the layout.

 

For example:

 

- The G and S pins are shorted together.

- The D pin is connected to a large copper area instead of a trace connecting it to the choke and to the boost diode ... this greatly increases the coupling of dv/dt noise into low voltage, high impedance circuitry in the vicinty

- I cannot find the bulk capacitor in the layout, nor the HV small bypass capacitor for reducing the "loop area", which is electrically in parallel with the bulk capacitor

 

 And, please post a schematic.

Sorry I think the image of the layout was not clear.

 - Pins G and S are not shorted together.

 - For D pin connection, you recomend a normal net instead a copper area. Ok, we will change it.

 - You will find the bulk cap in the new image attached.

 

See that the main problem of our design is the abaible area that we have in our PCB so we did de layout as good as we can. 

 

Thank you, 

Everyone has the same problem of "tight available area" but still, the layout is *critical*.  Your layout may need to be revamped. 

The PCB image you posted is such that one layer obscures all others. Other copper layers cannot be seen.  Can you set the PCB software to show all layers as semi-transparent?

In your schematic, C123 and C124 are shown as sitting close to the bulk cap.  In the layout they *MUST* be sitting close to the boost diode and the PFS, connected with short traces.  I can't find them in your layout image. 

 

I can't find the V, FB, and VCC pin bypass capacitors.  They *MUST* sit close to the device.

 

The Q18 and Q19 circuitry MUST be close to the device, AND situated far away from the Drain node which has very high dv/dt.  Nodes with high dv/dt will couple capacitively into all small-signal high impedance circuitry, of which the Q18/Q19 circuitry is one.

Please find attached a pcb print pdf file. 

 

C123 and C124 thay are closed to bulk capacitor on bottom layer.

 

We will review all the points that you commented. 

 

Thank you, 

The purpose of C123 and C124 are not to bypass the bulk cap, but to act as a proxy for the bulk cap, (at high frequencies), close to the PFS and diode, in order to shrink the "loop area" formed by the PFS, diode, and capacitor(s), and their interconnects .  Without it the distant bulk cap greatly enlarges said area.  This cause large voltage spikes on the Drain pin and EMI and noise that will couple into adjacent circuits.

 

Pls. review the layout recommendations throroughly - in the datasheet, app note, and my previous posts.  Then fix your layout and report back. 

Hi,

 

we redesign the PCB according to all your recomendations. Could you please check again that we comply all routing considerations? Thanks a lot. 

From what I can see it's greatly improved.

 

Watch out for noise from the Drain node.  C51 is sitting very near a trace that is connected to Drain, which if noise sensitive, will be affected badly.  There are a bunch of components near C51, which is under what I think is the PFC choke.  The PFC choke can also couple noise into nearby sensitive circuits.

Hello,

 

we redesigned our layout according to your recomendations but we have still the same problem at 90VAC when trying to provide full power (350W).

 

At the beggining we though that we had a problem with the inductor but we have tested our inductor with your PFC evaluation board and it works perfectly.  

 

There is any other point that we should check? Thanks 

Pls. post latest layout and schematic.

Hi,

 

I think that we have a problem with grounds (G and S). In Application Note 51, page 31 there is a schematic with the same configuration that we are using (TFS + PFS). Do you think that the ground G is propertly returned? Thanks 

The schematic appears correct but what is important is the actual layout.

Pls. post the layout.

  

Find attached the layout. If you have any problem with the format file, please let me know. Thanks

Hi,

 

Please allow me to respond while my colleague is away.

 

I reviewed the layout and the schematic and I find a number of issues with this design.

 

The layout does not appear to follow many of our guidelines. The  PFC input and output traces appear to cross in a number of locations. The PFC feedback circuit which is a sensitive circuit, appears to be surrounded by the power circuit loops.

 

I will be happy to go over this layout with you which is perhaps best done over a WebEx meeting so that I can show you the multiple areas that need modification and explain the reasons. Alternately you can contact our Field sales office for field applications engineer support and our field applications engineer should be able to help you as well. This will be in your local language and may be more beneficial however I am happy to help as well.

 

Please let me know how you wish to proceed and I will setup a conference call/ WebEx meeting with one of oour factory applications engineers or myself.

 

Regards

PI-Sarek

Hi,

 

Finally we did a new layout reducing some non vital components (EMI Filter, Relay) in order to have more free room and have a better layout. By the moments it seems that it works but we haven't verified the full load condition yet. I will keep you informed of the results.

 

Thanks for the support. 

 

Regards, 

Sorry I think the image of the layout was not clear.

 - Pins G and S are not shorted together.

 - For D pin connection, you recomend a normal net instead a copper area. Ok, we will change it.

 - You will find the bulk cap in the new image attached.

 

See that the main problem of our design is the availabble area that we have in our PCB so we did de layout as good as we can. 

 

Thank you, 

Spreadsheet shows a huge gap.  You should run more turns and a higher flux density.

However, this is unlikely the cause of your failures.