We observe some strange behavior with a design with an InnoSwitch 3 Design.
The device stops increasing its switching frequency above 30kHz when further increasing the load, but instead of this, it adds bursts of switching at its highest frequency, leading to a high ripple of our output voltages.
The strange thing is, If we disconnect VOUT from 12V Output voltage, the behavior under load is as expected:
Frequency increases as specified smooth over 30kHz to round about 70kHz (@230V), maximum load can be drawn.
See named scope images in the attachment.
What we also observe is, that the voltage at the BPS capacitor shows a stairway behaviour when VOUT is connected to 12V. BPS voltage is smooth, when VOUT is disconnected, and the secondary is only supplied via FWD pin.
See also named scope images in the attachment.
Disconnecting VOUT is not an option, because the InnoSwitch will switch off, if the load is removed.
We just struggled over this behaviour when "debugging" the circuit.
Do you have any hints, what could go wrong in our design? We don't find any documentationon what circumstances jittering should stop. We also have no clue, why connecting VOUT to its desired connection will influence the under load condition. We tested several measures, but with the lack of knowledge what happens inside the chip it is pretty complicated.
If you need additional measurments or information, feel free to request them.
The design is a multiple output design, with a standard wide range input.
We have the following outputs:
The feedback resistor network is connected to the 12V rail.
All three output voltages are fed from different taps of one winding, the additional 24V are on a separate winding