LED output voltage oscillating at 0.5-0.1 Hz when using PWM dimming (LNK419) - Solved

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Hi,

I am using an RDR195 based design using a linkswitch PH (LNK419 for 32W operaton), setup for digital PWM dimming as explained in this post: "http://www.powerint.com/forum/power-supply-design/can-i-perform-pwm-dimming-using-linkswitch-ph" and the associated PDF. A 1:1000 dimming range is comfortably achieved, using a PWM frequency of 400 Hz. Full output is at 700mA

Oddly, we have noticed that at an approximate duty cycle of 7.5%, our LED output appears to be unstable by oscillating somewhere between 0.5 and 0.1Hz - often the frequency gradually shifts over a period of a few minutes! The attached image shows the secondary-side output voltage across the ripple-smoothing capacitors; the LED load is quite clearly showing to be 'pulsing'. This particular duty cycle appears to cause the most severe oscillations, and as duty cycle moves away from this value in either direction, the peak-peak voltage of the oscillations decrease. Outside the range of approximately 6-9% PWM duty cycle, the output voltage and LED brightness is considered sufficiently steady.

I've ensured a suitable heatsink is used and have tried removing the over-voltage circuit, with no improvements in the output oscillations. The PWM signal has been confirmed to be steady, and both a microcontroller and benchtop signal generator have been tried as the source. At lower PWM frequencies, the most severe oscillations seem to occur at lower duty cycles yet tend to show increased peak-peak voltages.

Has anyone experienced similar behaviour or have any suggestions for this odd issue? The low frequency/time constant of the output voltage make me think perhaps the feedback resistor (approx 120K) and either the bias winding or BP pin capacitor (22uF, 10uF) are possibly creating some sort of RC circuit here.

Kind Regards,
dave-ml

PI-Troi: no we haven't seen this kind of behavior yet. Can you also take a scope shot of the output current and drain voltage in the described condition? I suspect the device is going into auto-restart condition due to the current into FB pin falls below ~12uA. Would also send your schematic showing the pwm circuit.

Unfortunately, I haven't yet been able to obtain the output current waveform as requested, but should be able to post this tomorrow. In the mean-time, here is the PWM-section of the Linkswitch-PH419 circuit, and an oscilloscope screenshot of the drain-pin voltage whilst dimming at with a 7.6% duty cycle (where output fluctuations are most severe).

If I understand correctly, whilst in auto-restart mode, the Linkswitch PH will operate with a switching duty cycle of approx 3%. In brief testing, I was not able to see the drain voltage ever having a switching duty cycle of less than about 19%, as shown in the waveform. I will be able to verify later if the duty cycle ever fall below this.

Thank you for your help, it is much appreciated!
Regards,
dave-ml

Here is the LED driving current waveform as requested. A 1 Ohm series shunt resistor was used, so the image shows approximately 200mA per division.

I've also included an image showing the current waveform much further zoomed in. The pulse heights clearly rise and fall over time, as would be expected from seeing the first image.

Kind regards,
dave-ml

PI-Troi I reviewed your data although the schematic is incomplete it is hard to tell what is going on with your circuit without probing intensively into your circuit or set-up. Perhaps an analog dimming will work better on your application here is an acutal design that's been tried, built, and tested, here is the link http://www.powerint.com/sites/default/files/PDFFiles/der263.pdf

Thank you for having a look into the data. I appreciate the difficulty in working with an incomplete schematic - I am unable to post the full schematic due to the sensitivity of my project. If I were able to e-mail this to yourself, this might be a possibility.

Unfortunately the analog dimming is not an available option to me: the active-load puts efficiency out of requirements when dimming, yet the 1:1000 range is still required.

Regards,
dave-ml

Hi,
I had a PI reference design board (RDR194) available and wished to see if the LED oscillation appeared with digital PWM dimming on this also. The issue still appears in this circuit. I've attached a PDF showing the modified circuit used to test this out, along with oscilloscope readings for various voltages.

I've used 100Hz as the PWM frequency as this demonstrated more extreme oscillation than the 400Hz I had found the issue with in the first place. Increasing the frequency further does tend to reduce the oscillation - and in my application a higher PWM frequency is fine - but I'd like to ensure there isn't some underlying problem with my logic and circuit here before proceeding further.

For curiosity's sake, I have tried using DC battery packs in lieu of: the bias winding to supply current to the BYPASS circuit; the FEEDBACK circuit; and both circuits. In all cases, the full-output currents were correct and constant, but the oscillation issue still occurs.

I hope using a reference board for this issue helps out.

Is there an upper or lower limit recommended for the digital PWM frequency?

Regards,
dave-ml

To follow on from this, I've also measured the drain-source voltage as you'd suggested in your initial post and attached the waveforms for this at 100Hz PWM dimming with the modified RDR194 circuit, and at 2KHz for comparison. It is clear that with the 100Hz PWM frequency, the drain-source voltage waveform is changing over time (this was seen to coincide with the output oscillation).

I began to think with the input frequency being 50Hz (100Hz ripple after rectification) and a low duty cycle of 7.6%, the linkswitch-PH would only be able to switch the drain to source for 7.6% of the time. No doubt this 'switching' window would gradually shift along the rectified mains voltage over time as the PWM signal and rectified mains input are at virtually the same frequency but would not be exactly in sync and therefore would drift apart. Could this possibly be a cause of the output oscillation seen? If this were the case, this would certainly explain why higher PWM frequencies to reduce the level of oscillation observed.

Regards,
dave-ml

Just to confirm, the shifting of the 'drain switching-cycle window' (ie not in skip-cycle mode) with respect to the mains input voltage has been verified as the cause of the output voltage oscillations.

Looking at voltage waveforms, it is clear that output voltage/current is lowest when the drain is switching in the period where the rectified mains is at its lowest - and vice versa. When the digital PWM signal is synchronised to the mains input frequency through zero crossing detection, the output demonstrates normal behaviour.

Thank you for your time in looking into this issue,
dave-ml