Topswitch devices and the di/dt in the internal FET?

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Actually ive just done a Flyback design on the Power integrations PI Expert software, and at max vin , PI Expert did a design  that has  a primary di/dt of 670mA/us even though the datasheet of topswitch-jx page 27 states “270mA/us” for the TOP264 that PI Expert  software selected.

So it “appears” that you can have a primary di/dt above what the datasheet states, but who knows how far above it one can go, and what it means in terms of actual peak current limit ?..please advise?

Do we presume we take the 100ns current sense delay and assume  we can extrapolate linearly upwards by using that to get the peak current limit at higher di/dts than the datasheet states?