Explanation of layout considerations
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Can someone please explain this one to me:
In the buck or buck-boost converter confi guration, since the SOURCE pins in LinkSwitch-TN are switching nodes, the copper area connected to SOURCE should be minimized to minimize EMI within the thermal constraints of the design.
Would it be correct to assume that if I use board material that has good thermal properties (such as aluminium), the copper connected to the source pin could be as little as possible (without ignoring the electrical requirements for track width, etc)?
You probably mean the Aluminium backed boards that are used in telecom bricks...
You have to remember that heat from within the IC still needs to come out of the package; and it can only do so through the Source pins. The increased copper area around the Source pins reduces the thermal impedence from the case to ambient thereby reducing the operating temperature of the LinkSwitch. So I dont think that using this material you will be able to reduce this copper area.
Hi David,
All recommendations are very much standard PCB rules for signal reading, noise reduction, and power transfer.
Rule one applies to high current switching circuits. If the traces connecting these circuits are too long, we will get big voltage spikes along the PCB traces. Obviously, the PCB trace has a very low resistivity for DC currents. This is not at all the case when you have high frequency power switches with fast raising/falling edges. For this case, any extra length of a PCB connection will increase significantly the complex impedance of that trace; hence huge parasitic high frequency voltage spikes will be generated. This will affect not only the trace involved, but you will get a whole bunch of bonus problems: big overall EMI, big voltage and/or current ripple, parasitic voltage spikes transferred to other noise sensitive circuits.
The very same reasoning applies to rule number two, but in this case you have the victim circuit. For proper functionality, LinkSwitch-TN needs a very clean and stable voltage between BP and S pins. C1 is supposed to help achieve this goal, “closing the loop” for internal power transfer inside the chip: internal power sources and references. If this capacitor is not close to the decoupled pins, the voltage spikes could degrade the precision and functionality.
With rule three, the intent is to minimize the noise transfer between the power switching circuits and the AC lines. So, we have to keep these two circuits as far as possible. On the other hand, we need to make the final product as small as possible. We tried to offer an optimized noise/size solution, and the guidelines from our reference design must be followed as much as possible, unless you have the resources to play around with the geometry and retest the overall noise performance.
Rule four is a very good practice for noise reduction: keep the return trace (Neutral) as close and parallel as possible to the input trace (Line) to minimize the equivalent inductive loop; place the decoupling capacitors C4 and C5 between AC input and the noise source, in this case LinkSwitch-TN.
Rule five for the optional diode D4 applies to ESD and Surge events. The AC input is rectified trough D3 and the DC component stored on C4. For example, for 240Vac input, we can get up to 330Vdc on C4. When a high negative voltage event appears at the AC input, we can get way more than 700V negative voltage on Anod D3. Because the Cathode is already connected to positive 330V, the reverse voltage applied to D3 could greatly exceed the maximum rating. In this case, the extra diode D4 will keep the circuit safe even for 2000V reverse voltage events. By measuring the EMI signature, we identified a second benefit for using this extra diode: a slight noise reduction.
Cheers,
PI_Crusher