Corrective action needed for Pi warning about BVDSS , VUVON_Max and VOR

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I am designing a DC/DC converter using PI expert tool. and After I entered my design parameters, I got the following warning:

"Verify BVDSS during line surge, decrease VUVON_Max or reduce VOR"


I have 2 questions:

1- what does this mean? and what is the expected impact for this?

2- what is the corrective action that I need to do? if I understand well, then this problem can be solved by adding a varasitor, and connectinf it with a in series,  to prevent this surge , is this solution valid?





1. The drain voltage turn off ring for your design is very close to the breakdown of the MOSFET. This is the reason you need to reduce your VOR.

2. This warning does not imply a surge event, it points out to the voltage stress on the MOSFET. Changing the primary clamp or using a low primary leakage inductance transformer are the solutions to avoid a MOSFET breakdown. The varistor will only help during a surge, not steady state.

I reduced the VOR so much (even down to 10 volts! ) and this warning did not disappeared. It disappeared only when I disabled the "Undervoltage On Enable" checkbox. this also permitted me to to have reasonable values for overvoltage (The "Overvoltage Off Max" was 787 volts before I disable the "Undervoltage On Enable", and it became 423 volts after I disable. the value of 423 is more resonable for an overvoltage condition). In addition, the Overvoltage parameters became editable after I disabled "Undervoltage On Enable".am I on the right track now?


 please look at my attached design file.

DC-DC converter supply.uds470.5 KB

Seems like you are designing a high-line power supply with a narrow UV and OV range. The undervoltage and overvoltage currents are predetermined and hence, once you set the Vpin resistor, the OV/UV setpoints are fixed. If your objective is to achieve UV only, you can disable OV and vice versa (page 13 If you want both UV and OV, you will need an external sense circuit.